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.LM 10 .CHAPTER CHAPTER-VII VII. INSPECTION ELECTRONICS .SKIP 2 A. SIGNAL NAMING CONVENTIONS .SKIP 2 A.1 ANALOG SIGNALS .SKIP 2 A.2 DIGITAL SIGNALS .SKIP 2 B. DEFINITIONS .SKIP 2 C. CHANNEL DRAWER-ANALOG SECTION .SKIP 2 C.1 PRE-AMPLIFIER .SKIP 2 C.2 WIDE BAND DISCRIMINATOR CARD .SKIP 2 C.3 SCAN AMP RESTORER CARD .SKIP 2 C.4 AUTOCAL CARD .SKIP 2 C.5 DEFECT SIZE DISCRIMINATOR CARD .SKIP 2 C.6 LARGE HOLE DETECTOR CARD .SKIP 2 C.7 LARGE HOLE SIZE DISCRIMINATOR CARD .SKIP 2 C.8 LARGE CLUMP SIZE DETECTOR CARD .PAGE D. DIGITAL SECTION-TIMING AND GATE GENERATION .SKIP 2 D.1 REFERENCE SIGNALS .SKIP 2 D.2 INTERVALS AND EVENTS .SKIP 2 D.3 TYPICAL DECODER .SKIP 2 D.4 DECODE ZERO .SKIP 2 D.5 DECODE SELECTION .SKIP 2 D.6 COUNTER OPERATION .SKIP 2 D.7 INTERVAL ZERO GENERATION .SKIP 2 D.8 END-OF-TIME-PERIOD PULSES .SKIP 2 D.9 INTERVAL A AND B GENERATION .SKIP 2 D.10 INTERVAL C AND D GENERATION .SKIP 2 D.11 COUNTER ENABLING .SKIP 2
D.12 COUNTER LOADING .SKIP 2 D.13 GATE GENERATION .PAGE E. DEFECT GATING .SKIP 2 E.1 PRODUCT GATE .SKIP 2 E.2 PRODUCT SELECT SWITCH .SKIP 2 E.3 LANE ENABLE GATES .SKIP 2 F. DEFECTIVE FOOT ZONE BUFFERS .SKIP 2 H. LARGE HOLE .SKIP 2 I. LARGE CLUMP .SKIP 2 J. ALARM RELAY BOX .SKIP 2 K. COMPUTER INTERFACE .SKIP 2 L. DEFECTIVE FOOT ZONE RATE COUNTER .SKIP 2 M. CONTROL AND ALARM .SKIP 2 FIGURE 7 ANALOG BLOCK DIAGRAM .SKIP 2 FIGURE 17 BASIC TIMING .SKIP 2 FIGURE 19 PRIMARY DECODE SELECTION .PAGE
.COMMENT PAGE 0 .PS 60 .HEADER TOP SPLIT RIGHT UPPER ARABIC .TITLE NP-8 SPUNLACED INSPECTION SYSTEM .SUBTITLE OPERATING AND MAINTENANCE MANUAL .LM 5 .RM 70 .SKIP 2 .CENTER VII. INSPECTION ELECTRONICS .BR .CENTER ---------------------------- .BR .SKIP 2 A. SIGNAL NAMING CONVENTIONS .BR ----------------------------- .SKIP 2 A.1 ANALOG SIGNALS .BR ------------------- .SKIP ANALOG SIGNALS ARE ASSUMED NORMALLY POSITIVE WITH RESPECT TO COMMON (E.G., 'GATED PA'). WHEN AN ANALOG SIGNAL IS INVERTED AND IS NEGATIVE WITH RESPECT TO COMMON, THE CHARACTERS 'INVERTED' ARE PREFIXED TO THE NORMAL SIGNAL NAME (E.G., 'INVERTED GATED PA'). .SKIP 2 A.2 DIGITAL SIGNALS .BR -------------------- .SKIP 2 DIGITAL SIGNALS ARE ASSUMED NORMALLY TRUE HIGH (E.G., 'RESET'). WHEN A DIGITAL SIGNAL IS INVERTED AND IS TRUE LOW, THE CHARACTERS '-NOT' ARE SUFFIXED TO THE NORMAL SIGNAL NAME (E.G., 'RESET-NOT'). .SKIP 2 B. DEFINITIONS .BR --------------- .SKIP 2 THROUGH OUT THIS DOCUMENT, MANY ABBREVIATIONS ARE USED WHICH ARE NOT NECESSARIALY EXPLAINED AT EACH USAGE. THIS SECTION DEFINES MANY OF THESE ACRONYMS AND ABBREVIATIONS, LISTED ALPHABETICALLY BELOW. .SKIP .LIST ACC AUTOCAL CARD .SKIP DFZ DEFECTIVE FOOT ZONE .SKIP DSD DEFECT SIZE DISCRIMINATOR .SKIP .PAGE ETP END-OF-TIME-PERIOD PULSES .SKIP IPE INSPECTION PERIOD ENABLE .SKIP LCSD LARGE CLUMP SIZE DETECTOR .SKIP LHD LARGE HOLE DETECTOR .SKIP LHSD LARGE HOLE SIZE DETECTOR .SKIP LLE LANE LOGIC ENABLE .SKIP MHZ MEGA HERTZ - 1 MILLION CYCLES PER SECOND .SKIP MSEC MILLISECOND - .001 SECONDS .SKIP NSEC NANOSECOND - .000 000 001 SECONDS .SKIP PA PRE AMP AS IN 'PA PEDESTAL' .SKIP PAS PROCESSED ANALOG SIGNAL .SKIP SAR SCAN AMP RESTORER CARD .SKIP USEC MICROSECOND - .000 001 SECONDS .SKIP WDB WIDEBAND DISCRIMINATOR CARD .SKIP .END LIST .PAGE
.COMMENT PAGE 1 C. CHANNEL DRAWER-ANALOG SECTION .SKIP 2 ENGINEERING DRAWINGS 2318M730 AMD 2417M737 DESCRIBE THE ANALOG SECTION OF EACH CHANNEL DRAWER. OTHER PRINTS REFERENCED IN THE SECTION THAT FOLLOW DESCRIBE INDIVIDUAL ANALOG CARDS USED IN THE ANALOG SECTION OF THE CHANNEL DRAWER. FIGURE 7 IS A BLOCK DIAGRAM SHOWING MAJOR SIGNAL FLOW WITHIN THE ANALOG SECTION OF THE CHANNEL DRAWER. THE DESCRIPTION OF THE ANALOG SECTION WHICH FOLLOWS IS ORGANIZED INTO DESCRIPTIONS OF INDIVIDUAL ANALOG CARDS. .SKIP .PAGE .CENTER FIGURE 7 .PAGE
.COMMENT PAGE 2 C.1 PRE-AMPLIFIER UNIVERSAL CARD (PAU-2) .BR --------------------------------------------- .SKIP 2 REFERENCE: 2318M738 .SKIP 2 THE PHOTOMULTIPLIER TUBE OUTPUT IS A CURRENT PROPORTIONAL TO THE INTENSITY OF THE LIGHT INCIDENT ON THE TUBE'S CATHODE. OPERATIONAL AMPLIFIER U5 CONVERTS THE CURRENT FROM THE TUBE TO THE NOMINALLY .33 VOLT 'COMPOSITE PA' SIGNAL. R8 SETS THE GAIN AND C5 ASSURES THE STABILITY OF OP-AMP U5. .SKIP TWO FUNCTIONS ARE SUBSEQUENTLY PERFORMED ON THE 'COMPOSITE PA' SIGNAL: .SKIP .LIST .INDENT -3 1.#OP-AMP U3 AND BUFFER AMPLIFER U1, WITH R18 AND R19 CHOSEN FOR A GAIN OF 3, INVERT THE SIGNAL, PROVIDING 'INVERTED COMPOSITE PA' WHICH IS TRANSMITTED TO THE INSPECTION CHANNEL DRAWER (WDB CARD IN THE ANALOG SECTION) THROUGH A 100-OHM TWISTED-PAIR SHIELDED TRANSMISSION LINE. OP-AMP U6, CONNECTED AS A NON-INVERTING UNITY GAIN VOLTAGE FOLLOWER, BUFFERS 'INVERTED COMPOSITE PA' TO THE 'PA' TEST JACK ON THE PM HOUSING. .SKIP .INDENT -3 2.#FOR AUTOMATIC GAIN CONTROL (AGC) THE 'COMPOSITE PA' SIGNAL (.33 VOLTS NOMINAL) IS SUMMED WITH THE VOLTAGE DEVELOPED BY R9 AND R10 (APPROXIMATELY .33 VOLTS). WHENEVER TRANSISTOR Q2 IS GATED ON, THE RESULT OF THE SUMMATION IS APPLIED TO THE INVERTING INPUT OF OP-AMP U7, SET UP AS AN INTEGRATOR. IF THE SUMMATION IS LESS THAN THE REFERENCE, THE OUTPUT OF OP-AMP U7 RISES, AND VICE VERSA. WHEN THE INPUT TO U7 IS ZERO, THE OUTPUT IS CONSTANT. TRANSISTOR Q1 FOLLOWS THE U7 OUTPUT AND DRIVES THE VENUS SCIENTIFIC MODEL K15 DC-TO-DC CONVERTER WHICH PRODUCES 100 VOLTS OUTPUT FOR EVER ONE VOLT INPUT, PROVIDING PM TUBE HIGH VOLTAGE. RESISTORS AND CAPACITORS ON THE SOCKET OF THE RCA C1764 PM TUBE BIAS THE DYNODES. AN INCREASE IN PM HIGH VOLTAGE CREATES MORE CURRENT FROM THE PM TUBE, RAISING 'COMPOSITE PA', THUS DECREASING THE DIFFERENCE BETWEEN 'COMPOSITE PA' AND THE REFERENCE, CAUSING LESS INCREASE IN HIGH VOLTAGE, ETC., UNTIL 'COMPOSITE PA' IS AT REFERENCE LEVEL. .SKIP .END LIST COMPARATORS U2-A AND U2-B GENERATE THE SIGNAL TO GATE ON Q2. U2-A IS CONNECTED AS A ZERO CROSSING DETECTOR. WHENEVER THE AC COUPLED 'COMPOSITE PA' SIGNAL IS ABOVE ZERO VOLTS THE OUTPUT OF U2 CHARGES C1. THE THRESHOLD ESTABLISHED BY R3 AND R6 IS SUCH THAT THE CHARGE ON C1 DOES NOT EXCEED THE THRESHOLD DURING THE AUTOCAL OR SELF-CHECK PORTION OF THE 'COMPOSITE PA'. THE PRODUCT PEDESTAL SEGMENT OF THE 'COMPOSITE PA' DOES CHARGE C1 SUFFICIENTLY TO EXCEED THE THRESHOLD AND U2-B THEN GATES ON TRANSISTOR Q2, ENABLING THE AGC CIRCUITRY. .SKIP TWO SCALING RESISTORS PROVIDE A MEASUREMENT OF PM HIGH VOLTAGE FOR TRANSMISSION TO THE CHANNEL DRAWER. A CURRENT OF 100 MICROAMPERES CORRESPONDS TO 1500 VOLTS DC. THIS MEASURE OF PM TUBE HIGH VOLTAGE DRIVES THE CHANNEL DRAWER PANEL METER. .SKIP
.COMMENT PAGE 3 .TEST PAGE 60 C.2 WIDEBAND DISCRIMINATOR CARD (WBD) .BR ------------------------------------------ .SKIP 2 REFERENCE: 2147M737 .SKIP 2 THE WBD CARD PERFORMS FOUR FUNCTIONS: .SKIP .LIST .INDENT -3 1.#BUFFERS THE 'INVERTED-COMPOSITE PA' FOR FUTHER PROCESSING AND DISTRIBUTION BY THE SAR CARD .SKIP R4 PROVIDES TERMINATION FOR THE TRANSMISSION LINE. OP-AMP U5 IS SET UP AS A NON-INVERTING BUFFER AND DRIVES PIN S2 WITH THE 'INVERTED-COMPOSITE PA'. .SKIP .INDENT -3 2.#AMPLIFIES AND INVERTS THE 'INVERTED-COMPOSITE PA' TO GENERATE 'CLAMPED PA' USED BY THE DIGITAL LOGIC .SKIP OP-AMP U6 IS SET UP AS AN INVERTING AMPLIFIER WITH A GAIN OF 4.5. OP-AMP U4 IS SET UP AS A NON-INVERTING BUFFER AND DRIVES PIN R2 WITH THE AMPLIFIED 'COMPOSITE PA'. THIS SIGNAL IS SHAPED TO FORM 'CLAMPED PA' BY AN M501 SCHMITT TRIGGER MODULE IN THE DIGITAL SECTION. .SKIP .INDENT -3 3.#BUFFERS THE 'PAS' (PROCESSED ANALOG SIGNAL) TO THE 'PAS' TEST JACK .SKIP OP-AMP U3 IS SET UP AS A NON-INVERTING BUFFER AND DRIVES PIN N2 WITH THE 'PAS'. .SKIP .INDENT -3 4.#COMPARES THE 'PAS' AGAINST THE 'SENSITIVITY' THRESHOLDS TO GENERATE THE +/- 'ALL DEFECT' SIGNALS .SKIP .END LIST COMPARATOR U1 IS SET UP TO DETECT 'PAS' SIGNALS THAT ARE MORE NEGATIVE THAN THE '- SENSIVITY' THRESHOLD SETTING. PIN J2 WILL BE HIGH WHENEVER THIS CONDITION EXISTS. COMPARATOR U2 IS SET UP TO DETECT 'PAS' SIGNALS THAT ARE MORE POSITIVE THAN THE '+ SENSITIVITY' THRESHOLD SETTING. PIN H2 WILL BE HIGH WHENEVER THIS CONDITION EXISTS. .SKIP
.COMMENT PAGE 4 .TEST PAGE 60 C.3 SCAN AMP RESTORER CARD (SAR) .BR ------------------------------------- .SKIP THE SAR CARD PROVIDES THREE FUNCTIONS: .SKIP 2 REFERENCE: 2147M737 .SKIP 2 .LIST .INDENT -3 1.#SUPPLIES SIGNALS TO THE PA TEST JACK AND THE UNIFORMITY ANALYZER .SKIP OP-AMP U6 IS SET UP AS AN INVERTING AMPLIFIER WITH A GAIN OF ONE. U6 INVERTS THE 'INVERTED-COMPOSITE PA' AND DRIVES PIN S2 WHICH IS CONNECTED TO THE PA TEST JACK. OP-AMP U4 IS SET UP AS AN INVERTING AMPLIFIER AND INVERTS THE OUTPUT OF U6 TO SUPPLY AN 'INVERTED-COMPOSITE PA' SIGNAL TO THE UNIFORMITY ANALYZER. .SKIP .INDENT -3 2.#DEVELOPE 'PAS' .SKIP THE NOMINALLY 1 VOLT DC VOLTAGE IS REMOVED FROM THE PEDESTAL BY A SWITCHED HIGH PASS FILTER, CONSISTING OF C12, R12 AND ANALOG SWITCH, U5. WHENEVER A 'TEST DEFECT GATE' OR A 'PRODUCT GATE' IS PRESENT AT PIN H2, THE ANALOG SWITCH (U5) IS OPEN ALLOWING THE AC OR INFORMATION SIGNALS TO PASS. WHEN THESE GATES ARE NOT PRESENT AT PIN H2 THE ANALOG SWITCH IS CLOSED SHORTING THE OUTPUT OF THE HIGH PASS FILTER TO GROUND. THE TIMING OF THESE GATES IS SUCH THAT THE OUTPUT OF THE HIGH PASS FILTER IS SHORTED TO GROUND DURING THE 1 VOLT TRANSISIONS OF THE 'COMPOSITE PA' SIGNAL. OP-AMP U1 IS SET UP AS A NON-INVERTING BUFFER AND DRIVES OP-AMP U2. U2 IS SET UP AS A DIFFERIENTIATOR AND SUPPLIES THE 'PAS' TO THE WBD CARD. .SKIP .INDENT -3 3.# SUPPLIES A SIGNAL TO THE LHD CARD .SKIP OP-AMP U3 IS SET UP AS AN INVERTING FILTER. THE 'INVERTED-COMPOSITE PA' IS INVERTED AND SOME HIGH FREQUENCY INFORMATION REMOVED BEFORE DISCRIMINATION BY THE 'LARGE HOLE' AND 'LARGE CLUMP' CIRCUITS. .SKIP .END LIST
.COMMENT PAGE 5 .TEST PAGE 60 C.4 AUTOCAL CARD (ACC) .BR --------------------------- .SKIP 2 REFERENCE: 2147M737 .SKIP 2 THE ACC CARD DEVELOPES THE +/- SENSITIVITY THRESHOLD VOLTAGES. .SKIP A REGULATED DC VOLTAGE IS SUPPLIED TO THE +/- SENSITIVITY POTS, LOCATED ON THE FRONT PANEL OF THE CHANNEL DRAWER, FROM PIN P2 OF THE THE ACC CARD. OP-AMP IC4 IS SET UP AS A NON-INVERTING BUFFER AND DRIVES PIN H2 WITH THE '- SENSIVITY' THRESHOLD. OP-AMP IC6 IS ALSO SET UP AS A NON-INVERTING BUFFER AND DRIVES THE '- REF' TEST JACK. OP-AMP IC5 IS SET UP AS AN INVERTER AND DRIVES PIN J2 WITH THE '+ SENSITIVITY' THRESHOLD. THESE THRESHOLD LEVELS ARE USED ON THE WBD CARD.
.COMMENT PAGE 6 .TEST PAGE 60 C.5 DEFECT SIZE DISCRIMINATOR (DSD) .BR ---------------------------------------- .SKIP 2 REFERENCE: 2147M737 .SKIP 2 THE FUNCTION OF THE DSD CARD IS TO MEASURE THE DURATION OF THE '+ ALL DEFECTS' AND '- ALL DEFECTS' SIGNALS GENERATED BY THE WBD CARD. .SKIP SINCE THE OPERATION OF BOTH DSD CARDS IS IDENTICAL ONLY THE + DEFECTS WILL BE DESCRIBED. .SKIP IC3, R1 AND C2 FORM A SWITCHED INTEGRATOR CIRCUIT. IC1 IS SET UP AS A NON-INVERTING BUFFER AND PROVIDES THE GATE TO SWITCH ON ANALOG SWITCH IC3. WHEN THE '+ ALL DEFECTS' SIGNAL IS LOW THE ANALOG SWITCH IS CLOSED AND C2 IS SHORTED TO GROUND. WHEN THE '+ ALL DEFECTS' SIGNAL IS HIGH THE ANALOG SWITCH IS OPEN AND THE CHARGING PATH TO C2 IS ACTIVE. THE CHARGE ON C2 IS PROPORTIONAL TO THE DURATION OF THE '+ ALL DEFECTS'M SIGNAL. IF THE DURATION IS LONG ENOUGH THE CHARGE ON C2 WILL EXCEED THE '+ SIZE' DISCRIMINATOR THRESHOLD . THE OUTPUT OF IC2 WILL GO HIGH INDICATING A DEFECT TO BE PROCESSED BY THE DIGITAL CIRCUITS. .SKIP
.COMMENT PAGE 7 .TEST PAGE 60 C.6 LARGE HOLE DETECTOR (LHD) .BR ------------------------------ .SKIP 2 REFERENCE: 2147M752 .SKIP 2 THE FUNCTION OF THE LHD CARD IS TO COMPARE THE PEDESTAL SIGNAL AGAINST THE AMPLITUDE THRESHOLDS SET FOR THE DETECTION OF LARGE HOLES AND LARGE CLUMPS. .SKIP COMPARATORS U1 AND U2 RECIEVE A 'FILTERED PA' SIGNAL FROM THE SAR CARD. U1 COMPARES THIS SIGNAL AGAINST THE LARGE HOLE AMPLITUDE THRESHOLD. WHENEVER THE 'FILTERED PA' SIGNAL IS MORE POSITIVE THAN THE THRESHOLD PIN J2 WILL BE HIGH. U2 COMPARES THE 'FILTERED PA' SIGNAL AGAINST THE LARGE CLUMP AMPLITUDE THRESHOLD. WHENEVER THE 'FILTERED PA' IS MORE NEGATIVE THAN THE THRESHOLD PIN H2 WILL BE HIGH. .SKIP THE VOLTAGE REGULATOR ON THE LHD CARD ALSO SUPPLIES +/- 15 VOLTS TO THE POT CARDS E11 AND E7. .SKIP
.COMMENT PAGE 8 .TEST PAGE 60 C.7 LARGE HOLE SIZE DETECTOR (LHSD) .BR ------------------------------------ .SKIP 2 REFERENCE: 2147M752 .SKIP 2 THE FUNCTION OF THE LHSD CARD IS TO MEASURE THE DURATION OF THE LARGE HOLE DEFECT SIGNALS GENERATED BY THE LHD CARD. .SKIP THIS CARD IS IDENTICAL IN OPERATION TO THE DSD CARD DESCRIBED IN SECTION 3.A.5. .SKIP
.COMMENT PAGE 9 .TEST PAGE 60 C.8 LARGE CLUMP SIZE DETECTOR (LCSD) .BR ------------------------------------- .SKIP 2 REFERENCE: 2147M752 .SKIP 2 THE FUNCTION OF THE LCSD CARD IS TO MEASURE THE DURATION OF LARGE CLUNP DEFECTS GENERATED BY THE LHD CARD. .SKIP WITH THE EXCEPTION OF A DIFFERENT VALUE CAPACITOR FOR C2, PERMITTING CALIBRATION FOR SIGNALS OF LONGER DURATION, THIS CARD IS IDENTICAL IS OPERATION TO THE DSD CARD DESCRIBED IN SECTION 3.A.5. .SKIP .PAGE
D. DIGITAL SECTION-TIMING AND GATE GENERATION .BR -------------------------------------------------- .BLANK 2 D.1 REFERENCE SIGNALS .BREAK ------------------------- .BLANK ALL TIMING IS INITIALLY GENERATED BY THE 'END OF SCAN' AND 'CLAMPED PA' SIGNALS. THE 'END OF SCAN' SIGNAL, GENERATED JUST AFTER THE PRODUCT IS SCANNED, INITIALIZES TIMING. FOR DESCRIPTIVE PURPOSES, IT IS CONSIDERED THE FIRST PULSE IN THE TIMING SEQUENCE. THE 'CLAMPED PA' SIGNAL INITIATES SUBSEQUENT TIMING EVENTS ON THE NEXT SCAN. THIS SIGNAL HAS TWO COMPONENTS, THE 'TEST DEFECT' PULSE AND THE 'PRODUCT PEDESTAL'. .BLANK 2 D.2 INTERVALS AND EVENTS .BREAK ---------------------------- .BLANK ALL LOGIC FUNCTIONS OCCUR IN FIVE DISCRETE NON-OVERLAPPING INTERVALS AS SHOWN IN FIGURE 17. INTERNAL TIMING, GENERATED USING A 3.346 MHZ CLOCK AND REFERENCED TO THE BEGINNING OF EACH INTERVAL, IS USED TO GENERATE SPECIFIC EVENTS WITHIN EACH INTERVAL. .BLANK INTERVAL 0 EVENTS INITIALIZE VARIOUS TIMING CIRCUITS, STORE PRODUCT WIDTH INFORMATION FROM THE PREVIOUS SCAN, AND START INTERVAL A. .BLANK INTERVAL A AND B ARE GENERATED BY BUT NOT USED BY THIS INSPECTION SYSTEM. .SKIP INTERVAL C EVENTS GENERATE THE 'TEST DEFECT GATE' AND PREPARE INTERVAL D FOR INITIATION. .SKIP INTERVAL D IS INITIATED AND TERMINATED BY THE PRODUCT PEDESTAL. DURING THIS INTERVAL, INSPECTION GATES FOR THE ANALOG SECTION ARE GENERATED AND PRODUCT WIDTH IS DETERMINED. .PAGE
.CENTER FIGURE 17: BASIC TIMING .CENTER --------------------------- .PAGE
D.3 TYPICAL DECODER .BR ----------------------- .SKIP 2 BASIC EVENTS FOR EACH INTERVAL ARE GENERATED USING M236 UP/DOWN COUNTERS AND LOGIC GATE DECODERS (2147M733). THE UP COUNTER IS INITIATED AT THE START OF INTERVALS A, B, C, AND D. IT INCREMENTS FOR EACH CLOCK PULSE AND ACTIVATES THE OUTPUT OF EACH DECODER AT ITS PRESELECTED COUNT. IN THE EXAMPLE OF DECODE '0032' (2147M733), A COUNT OF 32 (DECIMAL) PRODUCES A 'HIGH' ON THE '32' BIT WITH 'LOWS' ON ALL OTHER BITS, RESULTING IN 'LOW' AT D10P2 AND A 'HIGH' AT D13F1 FOR DECODE '0032'. THE RESULTING 'HIGH' OUTPUT LASTS FOR 298 NSEC (1 COUNT OF 3,346 MHZ CLOCK) AND, IN THIS CASE, IS NAMED 'DECODE 2'. IT REOCCURS 9.5 USEC (32 * 298 NSEC) AFTER THE START OF EACH INTERVAL. BY COMBINING THIS PULSE WITH INTERVAL ENABLE GATES, SPECIFIC EVENTS CAN BE GENERATED. FOR EXAMPLE, 'C ENABLE' AND 'DECODE 2' ARE LOGICALLY 'NANDED' TO PRODUCE EVENT 'C2' WHICH RESETS THE 'TEST DEFECT GATE' (2147M734). .BLANK SEPARATE DECODERS MONITOR THE UP COUNTER PRODUCING 'DECODE 1', 'DECODE 2', 'DECODE 3', AND 'DECODE 4'. 'DECODE X' AND 'DECODE Y' ARE PRODUCED IN A SIMILAR MANNER BY A DOWN COUNTER. 'DECODE 0', PRODUCED IN A NON-TYPICAL MANNER, IS DESCRIBED BELOW. .BLANK 2 D.4 DECODE ZERO (LSB) (2147M734) .BREAK ------------------------------ .BLANK DECODE ZERO IS USED DURING INTERVAL C. WHEN THE UP COUNTER IS ENABLED, THE FIRST CLOCK PULSE SETS THE 1 OUTPUT OF THE COUNTER. THIS OUTPUT PULSE IS 'NANDED' WITH THE 'C ENABLE' SIGNAL TO SET AN R/S FLIP -FLOP (C18H2). WHEN THE 0 OUTPUT OF THAT FLIP-FLOP GOES LOW (C18J2), THE SECOND FLIP-FLOP IS SET (C18S2 GOES LOW) DISABLING THE INITIAL NAND GATE (C17V2 GOES HIGH). SUBSEQUENT PULSES FROM THE UP COUNTER ARE IGNORED DURING THIS INTERVAL. THUS, ONLY THE FIRST OUTPUT PULSE PASSES THROUGH THE GATE TO PRODUCT THE EVENT 'C0-NOT'. .BLANK 2 D.5 DECODE SELECTION .BREAK ------------------------ .BLANK THE PARTICULAR COUNT VALUES WHICH ACTIVATE EACH DECODER ARE SHOWN IN FIGURE 19. THEY WERE SELECTED TO PRODUCE THOSE EVENTS WHICH REQUIRE PRECISE TIMING IN A PARTICULAR INTERVAL. ONCE SELECTED, A DECODE PULSE MAY BE USED IN OTHER INTERVALS WHERE PRECISE TIMING IS NOT REQUIRED. .BLANK SELECTION OF DECODES 0 AND 2 IS DETERMINED BY THE REQUIREMENT THAT 'TEST DEFECT GATE' MUST OCCUR WITHIN THE 'TEST DEFECT' PULSE. THEREFORE, DECODE 0 OCCURS ONE CLOCK PULSE AFTER THE LEADING EDGE OF THE PULSE AND DECODE 2 IS GENERATED 32 COUNTS INTO INTERVAL C. THIS OCCURS JUST BEFORE THE TRAILING EDGE OF THE 'TEST DEFECT' PULSE. .BLANK DECODE 1 IS CHOSEN TO PRODUCE EVENT D1 SO THAT IT STARTS THE 'PRODUCT GATE' 6 COUNTS AFTER THE LEADING EDGE OF THE PEDESTAL. .BLANK DECODE 3 IS CHOSEN TO GENERATE THE C3 EVENT JUST AFTER THE TEST DEFECT PULSE AND TO BE CONSISTENT WITH INTERVAL D REQUIREMENTS FOR GENERATING THE 'PRODUCT GATE' SIGNAL USED BY THE ANALOG SECTION. .BLANK DECODES X IS GENERATED BY A TYPICAL DECODER WHICH MONITORS THE DOWN COUNTER. INITIALLY THIS COUNTER CONTAINS THE NUMBER OF PULSES COUNTED BY THE UP COUNTER DURING THE PREVIOUS SCAN. DECODE X IS GENERATED WHEN THE DOWN COUNTER CONTAINS A COUNT OF 6. .BLANK .PAGE
.CENTER FIGURE 19: PRIMARY DECODE SELECTION .CENTER --------------------------------------- .PAGE
D.6 COUNTER OPERATION (2147M733) .BREAK ------------------------------------ .BLANK INPUT LINES TO THE UP COUNTER ARE CONNECTED TO GROUND SO THAT THE COUNTER IS ZEROED WHEN 'LOAD UP-NOT' IS GENERATED. 'LOAD UP-NOT' IS GENERATED AT THE END OF EVERY INTERVAL EXCEPT INTERVAL D. 'ENABLE UP' (GENERATED DURING ALL INTERVALS EXCEPT INTERVAL 0) ACTIVATES THE COUNTER. NEITHER THE UP NOR THE DOWN COUNTER IS ENABLED DURING INTERVAL 0 SO THAT THE CONTENTS OF THE UP COUNTER CAN BE TRANSFERRED TO THE DOWN COUNTER AS A MEASURE OF PRODUCT WIDTH ON LAST SCAN. 'LOAD DOWN-NOT' TRANSFERS THE D INTERVAL COUNT, WHICH CORRESPONDS TO THE PRODUCT WIDTH, TO THE DOWN COUNTER. THE 'ENABLE DOWN' SIGNAL (GENERATED DURING INTERVAL D) THEN PERMITS CLOCK PULSES TO DECREMENT THE DOWN COUNTER. THIS TECHNIQUE PERMITS THE SYSTEM TO ADAPT TO DIFFERENT PRODUCT WIDTHS. FOR WIDER PRODUCT, EXTRA COUNTS WILL BE ACCUMULATED BY THE UP COUNTER DURING THE SCAN. ON THE NEXT SCAN THE DOWN COUNTER SUBTRACTS THE SAME NUMBER OF EXTRA COUNTS PRODUCING 'DECODE X' AND 'DECODE Y' IN THE PROPER POSITIONS. .BLANK 2 D.7 INTERVAL ZERO GENERATION (2147M734) .BREAK ------------------------------------------- .BLANK THE 'END OF SCAN' SIGNAL INITIATES INTERVAL 0 BY DRIVING C10B1 LOW. USED AS THE CLOCK INPUT TO AN M207 J/K FLIP-FLOP, THIS SETS THE OUTPUT C10E1 HIGH BECAUSE THE J INPUT IS AT +3 VOLTS AND THE K INPUT IS GROUNDED. .BLANK THE STATE OF OUTPUT C10E1 CONTROLS THE SECOND J/K FLIP-FLOP. WHEN C10E1 IS LOW, THE SECOND FLIP-FLOP IS KEPT IN A RESET STATE. AS SOON AS C10E1 GOES HIGH, THE J INPUT OF THE SECOND FLIP-FLOP (C10R1) IS ACTIVE AND THE NEXT HIGH-TO-LOW TRANSITION OF THE CLOCK WILL SET THE OUTPUT OF THE SECOND FLIP-FLOP (C10S1) HIGH. THE M113 NAND GATE OUTPUT, D15S2, GOES LOW FOR THE FOLLOWING CLOCK PULSE, PRODUCING THE 'START ETP-NOT' SIGNAL. THIS RESETS THE FIRST FLIP-FLOP (C10E1) WHICH IN TURN DIRECTLY RESETS THE SECOND FLIP-FLOP (C10S1). .BLANK 2 D.8 END-OF-TIME-PERIOD (ETP) PULSES (2147M734) .BREAK -------------------------------------------------- .BLANK A SERIES OF ETP PULSES ARE GENERATED TO INITIALIZE AND ENABLE THE UP AND DOWN COUNTERS AT THE END OF INTERVALS 0, A, B, AND C. THE PULSES ARE INITIATED BY 'START ETP-NOT' DURING INTERVAL 0 AND BY 'DECODE 3' DURING INTERVALS A, B, AND C. .BLANK THE 'START ETP-NOT' SIGNAL IS INVERTED BY M111 INVERTER C13R2, ACTIVATING THE M112 NOR GATE OUTPUT C14S1, WHICH SETS THE R/S FLIP-FLOP C18C1. 'DECODE 3-NOT' CAN ALSO SET C18C1 EXCEPT DURING INTERVAL D. DURING INTERVAL D, THE 'D READY' SIGNAL IS HIGH PREVENTING 'DECODE 3' FROM ACTIVATING C14N2. DURING INTERVALS A, B, AND C, 'D READY' IS LOW, WHICH NANDS WITH 'DECODE 3-NOT' TO PRODUCE A HIGH ACTIVE OUTPUT AT C14N2. THIS ACTIVATES C14S1, SETTING FLIP-FLOP C18P1 HIGH. .BLANK WHEN THE R/S FLIP-FLOP C18P1 IS HIGH, BOTH THE J/K INPUTS OF THE NEXT FLIP-FLOP ARE HIGH. EACH SUBSEQUENT CLOCK PULSE ON C15C1 THEN TOGGLES C15V2. THE FIRST CLOCK PULSE PRODUCES A HIGH, THE SECOND PRODUCES A LOW, ETC. THE RESULT IS THE 'ETP 1' SIGNAL WHICH COUPLES TO THE J/K INPUTS OF THE THIRD FLIP-FLOP (C15H2 AND K2, C15K1). .BLANK WHEN THE INPUTS OF THE THIRD FLIP-FLOP ARE HIGH, THE CLOCK PULSES TOGGLE THIS FLIP-FLOP AS WELL, PRODUCING SIGNAL 'ETP 2' AT C15T2. .BLANK 'ETP 1', 'ETP 2', AND THE CLOCK COMBINE TO ENABLE THE M115 NAND GATE (C11U1 GOES LOW), WHICH RESETS THE R/S FLIP-FLOP. PROPOGATION THROUGH THE M115 AND M203 RESULTS IN A 45 NSEC DELAY, PERMITTING THE TWO J/K FLIP-FLOPS TO TOGGLE TO THE LOW STATE AT THE SAME TIME THE R/S FLIP-FLOP IS BEING RESET. SUBSEQUENT CLOCK PULSES ARE NOT COUNTED AND THIS CIRCUITRY REMAINS INACTIVE UNTIL THE NEXT ETP SEQUENCE IS NEEDED. .BLANK 2 D.9 INTERVAL A _& B GENERATION (2147M734) .BREAK -------------------------------------------- .BLANK THE GENERATION OF THE INTERVAL 'ENABLE' SIGNALS REQUIRED TO ACTIVATE THE UP AND DOWN COUNTERS ARE DESCRIBED IN THIS AND THE NEXT SECTIONS. INTERVALS A _& B ARE DIRECTLY INITIATED BY ETP PULSES DESCRIBED EARLIER. INTERVALS C _& D, RESPECTIVELY, ARE INITIATED BY THE 'TEST DEFECT' AND 'PRODUCT PEDESTAL' COMPONENTS OF THE PA SIGNAL. SINCE ALL EVENTS ARE REFERENCED TO THE START OF AN INTERVAL, IT IS IMPORTANT THAT THE 'ENABLE' SIGNALS OCCUR AT THE SAME POINT OF EACH SCAN. .BLANK INTERVAL A IS SET UP FOR INITIATION BY 'START ETP-NOT' GENERATED IN INTERVAL 0. THIS SIGNAL SETS THE 'A INITIATE' FLIP-FLOP. 'A INITIATE' FLIP-FLOP OUTPUT, C12V1, NANDS WITH 'ETP 1' AND 'ETP 2' TO PRODUCE A LOW ACTIVE PULSE AT C11H2. THIS SETS THE 'A ENABLE' FLIP-FLOP PERMITTING THE UP COUNTER TO COUNT CLOCK PULSES. WHEN 'DECODE 1' OCCURS, EVENT 'A1-NOT' IS PRODUCED AT C11K1 AND THE 'A INITIATE' FLIP-FLOP IS RESET. 'ETP 1' AND 'ETP 2' PULSES IN OTHER INTERVALS THUS CANNOT SET THE 'A ENABLE' FLIP-FLOP. THE '0' OUTPUT OF THE 'A INITIATE' FLIP-FLOP IS USED TO RESET THE 'ENABLE DOWN' FLIP-FLOP AS DESCRIBED IN SECTION B.1.8. .BLANK EVENT 'A1-NOT', GENERATED AT C11K1, ALSO SETS THE 'B INITIATE' FLIP-FLOP IN PREPARATION FOR THE ETP PULSES AT THE END OF INTERVAL A. THESE PULSES TERMINATE INTERVAL A AND INITIATE INTERVAL B. 'ETP 1' AND 'ETP 2-NOT' ARE NAND'ED WITH THE 'CLOCK, PRODUCING A LOW ACTIVE PULSE AT C11D1, RESETTING THE 'A ENABLE' FLIP-FLOP. AFTER 400 NSEC, 'ETP 1' AND 'ETP 2' ARE ACTIVE AND COMBINE WITH 'B INITIATE' TO PRODUCE A LOW ACTIVE SIGNAL AT C11V1 WHICH SETS THE 'B ENABLE' FLIP-FLOP. THE '0' OUTPUT THEN GOES LOW RESETTING 'B INITIATE'. AT THE END OF INTERVAL B, THE ETP PULSES ARE GENERATED AGAIN. WHEN 'ETP 1' AND 'ETP 2-NOT' ARE BOTH HIGH, THE CLOCK PULSE PRODUCES A LOW SIGNAL AT C11D1 WHICH RESETS 'B ENABLE'. .BLANK 2 D.10 INTERVAL C _& D GENERATION (2147M734) .BREAK --------------------------------------------- .BLANK THE 'START ETP-NOT' PULSE PREPARES THE C INTERVAL FOR INITIATION BY RESETTING THE 'D READY' FLIP-FLOP. THE HIGH ON C12S2 AND THE NEXT COMPONENT OF THE 'CLAMPED PA' SIGNAL (WHICH IS 'TEST DEFECT') AT D20E2 COMBINE TO ACTIVATE C16F2. THIS LOW ACTIVE SIGNAL SETS THE 'C ENABLE' FLIP-FLOP (C12C1) AND THE 'D INITIATE' FLIP-FLOP (C12P1). .BLANK WHEN 'DECODE 3' OCCURS DURING INTERVAL C, THE ETP PULSES ARE GENERATED. 'ETP 1' AND 'ETP 2-NOT' COMBINE AS IN INTERVALS A _& B PRODUCING THE 'ENABLE RESET-NOT' SIGNAL WHICH CLEARS THE 'C ENABLE' FLIP-FLOP. THE SAME ETP PULSE COMBINATION COUPLED WITH 'D INITIATE' PRODUCES A LOW SIGNAL AT C11S2 WHICH SETS THE 'D READY' FLIP-FLOP. THE RESULTING HIGH SIGNAL AT C12R2 PERMITS THE NEXT COMPONENT OF THE 'CLAMPED PA' SIGNAL (WHICH IS THE PRODUCT PEDESTAL) TO PRODUCE A LOW OUTPUT AT C16F1, THE 'D ENABLE-NOT' SIGNAL. AS DISCUSSED EARLIER, THE 'D READY' SIGNAL DISABLES THE GENERATION OF ETP SIGNALS AT 'DECODE 3' OF INTERVAL D. INTERVAL D TERMINATES WITH THE PRODUCT PEDESTAL. .BLANK NOTE THAT THE '0' OUTPUT OF THE 'D READY' FLIP-FLOP, C12S2, ALSO RESETS THE 'D INITIATE' FLIP-FLOP AND DISABLES NAND GATE C16F2. .BLANK 2 D.11 COUNTER ENABLING (2147M734) .BREAK ----------------------------------- .BLANK 2 THE FOUR INTERVAL ENABLE SIGNALS (A,B,C,D) ARE NOR'ED TO PRODUCE THE 'ENABLE UP REQUEST' AT C17E1 IF ANY ENABLE SIGNAL IS ACTIVE. THE OUTPUT OF C17E1 CONTROLS A J/K FLIP-FLOP WHICH SYNCHRONIZES THE 'ENABLE UP REQUEST' SIGNAL WITH THE 'CLOCK'. WHEN C17E1 GOES HIGH, THE NEXT FULL CLOCK PULSE SETS C15R2. WHEN C17E1 RETURNS TO THE LOW STATE, THE K INPUT WILL BE HIGH. THE NEGATIVE TRANSITION OF THE NEXT CLOCK PULSE THEN RESETS C15R2 TO A LOW STATE. THE J/K FLIP-FLOP ASSURES THAT THE COUNTER IS NOT ENABLED OR DISABLED IN THE MIDDLE OF A CLOCK PULSE. A PARTIAL CLOCK PULSE CAN RANDOMLY CHANGE THE OUTPUT OF THE COUNTER DUE TO INSUFFICIENT INTERNAL PROPOGATION TIME. .BLANK 'ENABLE DOWN' IS INITIATED BY 'D ENABLE-NOT', WHICH SETS THE R/S FLIP-FLOP C12H2. C12H2 CONTROLS THE J INPUT AND C12J2 THE K INPUT OF THE 'ENABLE DOWN' FLIP-FLOP. AFTER C12H2 GOES HIGH, THE NEXT FULL CLOCK PULSE SETS C15N2. THE DOWN COUNTER CONTINUES COUNTING UNTIL 'A INITIATE-NOT' IS GENERATED BY 'START ETP-NOT'. THIS RESETS THE R/S FLIP-FLOP, C12H2 AND THE NEXT CLOCK PULSE DE-ACTIVATES THE 'ENABLE DOWN' FLIP-FLOP. .BLANK 2 D.12 COUNTER LOADING (2147M734) .BREAK ---------------------------------- .BLANK BEFORE THE COUNTERS ARE ENABLED, THEY MUST FIRST BE LOADED. THE DOWN COUNTER IS LOADED WITH THE CONTENTS OF THE UP COUNTER AND THE UP COUNTER IS 'CLEARED' BY LOADING ALL ZEROES. 'END OF SCAN' INITIATES THE ETP SEQUENCES WHICH PERFORMS THESE OPERATIONS. .BLANK 'START ETP-NOT' SETS C18F2 AND THE NEXT CLOCK TRANSITION GENERATES 'ETP 1' AND 'ETP 2-NOT'. THE 'LOAD DOWN-NOT' IS THEN ACTIVATED AND THE CONTENTS OF THE UP COUNTER ARE LOADED INTO THE DOWN COUNTER. THE SECOND CLOCK TRANSITION THEN PRODUCES 'ETP 1-NOT' AND 'ETP 2' WHICH ACTIVATES THE 'LOAD UP-NOT' GATE, CLEARING THE UP COUNTER. 'LOAD UP-NOT' ALSO RESETS C18F2. RECALL, HOWEVER, THAT 'LOAD UP-NOT' IS GENERATED AT THE END OF EACH INTERVAL EXCEPT INTERVAL D. .BLANK 2 D.13 GATE GENERATION (2147M734) .BREAK ---------------------------------- .BLANK THE GATES USED BY THE ANALOG AND DIGITAL DEFECT DETECTION CIRCUITRY ARE GENERATED BY SETTING AND RESETTING R/S FLIP FLOPS BY INTERVAL ENABLE SIGNALS AND COUNTER DECODE SIGNALS. MOST GATES ARE SET BY EVENTS GENERATED BY NAND'ING A PARTICULAR INTERVAL AND DECODE SIGNAL. GATES ARE USUALLY RESET BY A DECODE ALONE. .PAGE
E. DEFECT GATING .BR ------------------- .SKIP 2 THE PURPOSE OF THE DEFECT GATING CIRCUITS IS TO: .SKIP .LIST .INDENT -3 1.#CLASSIFY DEFECTS INTO EITHER THE MAJOR OR CRITICAL CATEGORY .SKIP .INDENT -3 2.#INDICATE WHICH LANE THE DEFECT OCCURRED IN .SKIP .INDENT -3 3.#CONVERT REAL TIME DEFECTS INTO DEFECTIVE FOOT ZONES (DFZ) .SKIP .INDENT -3 4.#PROVIDE LANE AND DFZ INFORMATION TO THE DEFECT RATE COUNTERS, THE PRINTERS IN THE REMOTE CONSOLE AND THE COMPUTER .SKIP 2 .END LIST E.1 PRODUCT GATE .BR -------------------- .SKIP 2 GENERATION OF THE PRODUCT GATE IS DESCRIBED IN SECTION .SKIP DEFECT SIGNALS ARE ANDED WITH THE 'PRODUCT GATE' TO ENABLE ONLY SIGNALS OCCURRING DURING THE TIME PERIOD OF THE 'PRODUCT GATE' TO BE CONSIDERED BY THE SUBSEQUENT LOGIC. .SKIP 2 E.2 PRODUCT SELECT SWITCH .BR ----------------------------- .SKIP 2 THE MAJOR AND CRITICAL CLASSIFICATION CRITERIA FOR FIVE DIFFERENT PRODUCT TYPES IS HARDWIRED VIA THE PRODUCT SELECT SWITCH. IN ADDITION, WHEN THE SWITCH IS IN THE COMPUTER MODE THE CLASSIFICATION IS UNDER COMPUTER CONTROL. MAJOR AND CRITICAL CLASSIFICATION DATA CAN BE SET UP OR ALTERED AS DESCRIBED IN SECTION II.H.5 OF THE OPERATORS MANUAL FOR THE SONTARA INSPECTION COMPUTER SYSTEM. THE FOUR TYPES OF DEFECT SIGNALS: .SKIP .LIST +TRANSMISSION .SKIP -TRANSMISSION .SKIP +REFLECTION .SKIP -REFLECTION .SKIP .END LIST CAN BE CLASSIFIED AS EITHER MAJOR OR CRITICAL. EACH POSITION OF THE PRODUCT SELECT SWITCH PROVIDES LOGIC SIGNALS THAT SELECTIVELY ENABLE THE DISCRIMINATOR OUTPUTS TO SET EITHER THE MAJOR DFZ BUFFER OR THE CRITICAL DFZ BUFFER. .SKIP 2 E.3 LANE ENABLE GATES .BR ------------------------- .SKIP 2 THE 'LANE ENABLE GATES' STEER THE MAJOR AND CRITICAL DEFECT SIGNALS TO THE PROPER DEFECTIVE FOOT ZONE BUFFER. THE SEQUENCE OF EVENTS THAT GENERATE THE 'LANE ENABLE GATES' IS AS FOLLOWS: .LIST .INDENT -3 1.#'LANE LOGIC ENABLE' SETS THE INSPECTION PERIOD ENABLE' (IPE) .SKIP .INDENT -3 2.#THE 'IPE' ANDED WITH THE 'PRODUCT GATE' ENABLES THE LANE COUNTER TO START COUNTING UP, AND STARTS 'LANE 1 ENABLE' .SKIP .INDENT -3 3.#WHEN THE COUNT IN THE LANE COUNTER EQUALS THE NUMBER SET IN THE "LANE BOUNDRY 1-2" THUMBWHEEL SWITCH 'LANE 1 ENABLE" ENDS AND 'LANE 2 ENABLE' BEGINS .SKIP .INDENT -3 4.#WHEN THE COUNT IN THE LANE COUNTER EQUALS THE NUMBER SET IN THE "LANE BOUNDRY 2-3" THUMBWHEEL SWITCH 'LANE 2 ENABLE" ENDS AND 'LANE 3 ENABLE' BEGINS .SKIP .INDENT -3 5.#THE PRODUCT GATE ENDS AND TERMINATES THE 'LANE 3 ENABLE' .SKIP .INDENT -3 6.#'END OF SCAN' RESETS THE 'IPE' FLIP-FLOP .SKIP 2 .END LIST
F. DEFECTIVE FOOT ZONE BUFFER .BR ---------------------------------- .SKIP 2 THERE ARE TWO DEFECTIVE FOOT ZONE BUFFERS, ONE FOR MAJOR AND ONE FOR CRITICAL DEFECTS. EACH 'DFZ' BUFFER CONSISTS OF THREE FLIP-FLOPS ONE FOR EACH LANE. THE BUFFERS ARE RESET ONCE EACH FOOT OF MD TRAVEL BY THE FOOT PULSE. IF ONE OR MORE DEFECTS OCCURRS DURING THE TIME PERIOD BETWEEN FOOT PULSES IT WILL SET THE 'DFZ' BUFFER. WHEN THE BUFFER IS RESET ANY FLIP-FLOPS THAT WERE SET WILL TRIGGER A 1 MSEC ONE SHOT WHICH PROVIDES AN OUTPUT TO THE 'DFZ' RATE COUNTERS, THE PRINTERS IN THE REMOTE CONSOLE AND THE COMPUTER INTERFACE BUFFER .NOTE NOTE: UP UNTIL THE 'DFZ' BUFFER, DEFECT PULSES ARE PRODUCED EVERY TIME A DEFECT IS SENSED; THEREFORE THESE PULSES ARE CALLED "REAL TIME" DEFECT DATA. THE 'DFZ' BUFFERS SENSE AND STORE ONLY THE FIRST REAL TIME DEFECT PULSE OCCURRING IN ANY ONE FOOT OF WEB TRAVEL. BECAUSE OF THIS THE OUTPUT PULSE IS TERMED A DEFECTIVE FOOT ZONE. THE RATE COUNTERS, PRINTERS AND COMPUTER SENSE DEFECTIVE FOOT ZONES NOT REAL TIME DEFECTS. .SKIP 2 .END NOTE H. LARGE HOLE .BR --------------- .SKIP 2 THE PURPOSE OF THE LARGE HOLE DIGITAL ELECTRONICS IS TO SOUND AN ALARM LOCATED IN THE REMOTE CONSOLE AND TO INFORM THE INSPECTION COMPUTER THAT A LARGE HOLE HAS OCCURRED. .SKIP DEFECT SIGNALS FROM THE LHSD CARD ARE SHAPED BY A SCHMIDT TRIGGER AND SET A DEFECTIVE FOOT ZONE BUFFER. SEE SECTION II.B.3. WHEN THE FOOT PULSE CLEARS THE 'DFZ' BUFFER TWO ONE SHOTS ARE TRIGGERED. ONE SETS A BIT IN THE COMPUTER INTERFACE BUFFER, THE OTHER OUTPUTS A 10 MSEC PULSE TO THE ALARM RELAY BOX. .SKIP I. LARGE CLUMP .BR ---------------- .SKIP THE PURPOSE OF THE LARGE CLUMP DIGITAL ELECTRONICS IS TO SOUND AN ALARM LOCATED IN THE REMOTE CONSOLE AND TO INFORM THE INSPECTION COMPUTER THAT A LARGE CLUMP HAS OCCURRED. .SKIP DEFECT SIGNALS FROM THE LCSD CARD ARE SHAPED BY A SCHMIDT TRIGGER AND SET A DEFECTIVE FOOT ZONE BUFFER. SEE SECTION II.B.3. WHEN THE FOOT PULSE CLEARS THE 'DFZ' BUFFER TWO ONE SHOTS ARE TRIGGERED. ONE SETS A BIT IN THE COMPUTER INTERFACE BUFFER, THE OTHER OUTPUTS A 10 MSEC PULSE TO THE ALARM RELAY BOX. .SKIP 2 J. ALARM RELAY BOX .BR -------------------- .SKIP 2 THE ALARM RELAY BOX IS LOCATED IN THE REAR OF THE MAIN CONSOLE. SIGNALS ENTERING THE BOX ARE OPTICALLY ISOLATED FROM THE CHANNEL DRAWER. THE LARGE HOLE AND LARGE CLUMP SIGNALS CLOSE THE APPROPRIATE RELAY WHICH PROVIDES A 110V SIGNAL TO THE PANALARM EQUIPMENT MOUNTED IN THE REMOTE CONSOLE. .SKIP 2 K. COMPUTER INTERFACE .BR ----------------------- .SKIP 2 REFERENCES: .LIST 2318M736 .SKIP 2318M753 .SKIP 2318M754 .SKIP .END LIST THE INTERFACE BETWEEN THE COMPUTER INPUT/OUTPUT AND THE INSPECTION ELECTRONICS IS THROUGH THE UDC8 UNIVERSAL INTERFACE LOGIC. A DETAILED DESCRIPTION OF THIS INTERFACE CAN BE FOUND IN THE VENDOR'S MANUAL DEC-08-H2DC-D. .SKIP ALL SIGNALS TO THE COMPUTER ARE DRIVEN BY M617 DRIVER CIRCUITS AND EXIT THE CHANNEL DRAWER ON J5. CONNECTOR J4 HANDLES ALL SIGNALS FROM THE COMPUTER. THESE SIGNALS GO DIRECTLY TO THE OPTICAL-ISOLATOR CIRCUITS IN THE CHANNEL DRAWER. THE OUTPUTS OF THE OPTICAL-ISOLATOR CIRCUITS ARE ONLY ENABLED WHEN THE PRODUCT SELECT SWITCH IS IN THE COMPUTER MODE .SKIP DETAILED DESCRIPTION OF THE COMMUNICATIONS BETWEEN THE INSPECTION ELECTRONICS AND THE INSPECTION COMPUTER CAN BE FOUND IN SECTION II.B OF THE OPERATORS MANUAL-SONTARA COMPUTER SYSTEM SOFTWARE. .SKIP 2
L. DEFECTIVE FOOT ZONE RATE COUNTER .BR ------------------------------------- .SKIP 2 THIS COUNTER IS A MODIFIED VERSION OF A HEWLETT-PACKARD 5330B PRESET COUNTER WITH INTEGERAL LIMIT SWITCH AND HI/LO OUTPUT RELAY (MODEL H45-5330B). A SEPARATE INSTRUCTION MANUAL FROM HEWLETT-PACKARD HAS BEEN SUPPLIED WITH THE INSPECTOR AND GIVES DETAILED INFORMATION ON THE THEORY AND OPERATION OF THE COUNTER. SECTION III, PAGES 3-12 OF THAT MANUAL DESCRIBES THE PROPER SETUP PROCEDURE FOR OPERATING THE COUNTER IN THE RATIO/TIME MODE OF OPERATION UTILIZED BY THE INSPECTOR. .SKIP THE PURPOSE OF THE COUNTER IS TO CALCULATE THE NUMBER OF DEFECTIVE FOOT ZONES PER "N" FEET OF WEB TRAVEL AND COMPARE THE RESULTS AGAINST A LIMIT "L1". IF THE 'DFZ' COUNT EXCEEDS "L1", THE COUNTER CAUSES THE 'DEFECT RATE ALARM' TO BE SET. BOTH THE NUMBER OF FEET OF WEB "N", AND THE DEFECT LIMIT "L1" ARE INDEPENDENTLY ADJUSTABLE FROM 1 TO 99,999. .SKIP WITH THE STORAGE SWITCH IN THE "OFF" POSITION, THE FOLLWING SEQUENCE WILL OCCUR: .LIST .INDENT -2 *#AT THE BEGINNING OF A NEW 80 FEET, THE DISPLAY IS RESET TO ZERO. .SKIP .INDENT -2 *#AS DEFECTIVE FOOT ZONES ARE ENCOUNTERED, THE DISPLAYED COUNT INCREMENTS. .SKIP .INDENT -2 *#WHEN THE DISPLAYED COUNT REACHES THE LIMIT "L1", THE ALARM WILL BE SET IMMEDIATELY. .SKIP .INDENT -2 *#THE DISPLAYED COUNT WILL CONTINUE TO INCREMENT UNTIL THE 80TH FOOT PULSE IS RECIEVED, THEN IT WILL RESET TO ZERO IN PREPARATION FOR THE NEXT 80 FEET OF PRODUCT. .SKIP .END LIST AN EXTERNAL RESET HAS ALSO BEEN PROVIDED TO RESET THE RATE COUNTER WHENEVER A DOFF OCCURS. .SKIP 2
M. CONTROL AND ALARM .BR ------------------------------ .SKIP 2 PARTS OF THIS SECTION CAN BE FOUND IN THE MAIN CONSOLE, REMOTE CONSOLE AND THE INSPECTOR FRAME. .SKIP CONTROL FUNTIONS CONSIST OF LASER "ON-OFF", SCANNER "STOP-START" AND SCAN MASKS "IN-OUT" PUSHBUTTONS, ALL OF WHICH ARE LOCATED ON THE MAIN CONSOLE CONTROL PANEL. SIX INDICATOR LIGHTS LABLED "DEFECT RATE", "UNIFORMITY", "INSPECTOR COOLING", "EDGE TEAR", "JET TRACK" AND "SELF CHECK", ALSO LCATED ON THIS PANEL, PROVIDE AN INDICATION OF THE CAUSE OF AN ALARM. THESE PUSHBUTTON INDICATORS ARE OF THE PRESS TO CLEAR TYPE. THE DRIVING LOGIC WILL NOT PERMIT AN ALARM TO BE CLEARED UNLESS THE ALARM CONDITION HAS BEEN ELIMINATED. .SKIP ALARM CONDITIONS SET FLIP-FLOP LATCHES AND TURN ON THE PROPER ALARM LIGHT ON THE CONTROL PANEL. AT THE SAME TIME A 'DOFF ALARM' SIGNAL IS SENT TO THE REMOTE CONSOLE WHERE IT SETS TWO FLIP-FLOPS. ONE, THE ALARM INDICATION FLIP-FLOP, DRIVES A HORN AND LIGHT IN THE REMOTE CONSOLE; THE OTHER, THE DOFF CONTROL FLIP-FLOP, ACTUATES THE DOFF RELAY. A ONE SHOT HOLDS THE DOFF RELAY CLOSED FOR 0.4 SEC. THIS IS THE AMOUNT OF TIME REQUIRED BY THE WINDUP CONTROLLER TO INITIATE THE WINDUP DOFF CYCLE. TWO FEATURES OF THIS SYSTEM SHOULD BE NOTED: .LIST .INDENT -2 *#NO MORE THAN ONE DOFF CYCLE CAN BE INITIATED BY THE INSPECTOR UNTIL THE OPERATOR RESETS THE DOFF CONTROL FLIP-FLOP. A LIGHTED PUSH BUTTON LABLED "RESET AUTO DOFF" WILL LIGHT TO REMIND THE OPERATOR OF THIS. .SKIP .INDENT -2 *#THE INSPECTOR DOFF RELAY, AS WELL AS THE AUDIBLE HORN, CAN BE DISABLED BY SWITCHES LOCATED IN THE REAR OF THE REMOTE CONSOLE. .SKIP 2 .END LIST .CHAPTER CHAPTER-VIII .PAGE